The present invention relates to a semiconductor device and a manufacturing technology thereof. In particular, the invention pertains to a semiconductor device obtained by forming a trench gate type power MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a Schottky barrier diode over one semiconductor substrate and a technology effective when applied to the manufacture of the semiconductor device.
Japanese Patent No. 2997247 (Patent Document 1) describes a technology of forming a trench gate type power MISFET, a clamping diode, and a Schottky diode over one semiconductor substrate. An object of this technology is to set the avalanche breakdown voltage of the clamping diode lower than the avalanche breakdown voltage of a body diode incorporated in the power MISFET, thereby improving the avalanche capability of the entire semiconductor device.
To fulfill the object, a heavily-doped epitaxial region (Nepi1) is formed over the semiconductor substrate (N+ substrate) and a lightly-doped epitaxial region (Nepi2) is formed over this heavily-doped epitaxial region (Nepi1) in Patent Document 1. A boundary between the heavily-doped epitaxial region (Nepi1) and the lightly-doped epitaxial region (Nepi2) is formed at a position deeper than the trench of the power MISFET. In a clamping diode formation region, a deep P+ layer (deep protective P+ diffusion portion 38) is formed and this deep P+ layer is brought into contact with the heavily-doped epitaxial region (Nepi1) to form a clamping diode having an avalanche breakdown voltage lower than the avalanche breakdown voltage of the body diode of the power MISFET.
In a Schottky barrier diode formation region, on the other hand, the Schottky barrier diode is made of the lightly-doped epitaxial region (Nepi2) and a metal layer (Schottky metal layer 41) formed over this lightly-doped epitaxial region (Nepi2). Also in this Schottky barrier diode formation region, a boundary between the lightly-doped epitaxial region (Nepi2) and the highly-doped epitaxial region (Nepi1) is formed at a position deeper than the trench of the power MISFET. Although the Schottky barrier diode is formed between trenches, the lightly-doped epitaxial region (Nepi2) formed between the trenches is fully depleted by decreasing the distance between these trenches. This improves the avalanche breakdown voltage of the Schottky barrier diode.
U.S. Pat. No. 6,351,018 (Patent Document 2) describes a technology of forming a trench-gate type power MISFET and a Schottky barrier diode over one semiconductor substrate. An object of the technology described in Patent Document 2 is to make an avalanche breakdown voltage of the Schottky barrier diode higher than the avalanche breakdown voltage of the power MISFET. In order to achieve this object, the distance between trenches having the Schottky barrier diode sandwiched therebetween narrower than the distance between the trenches having therebetween cells in which the power MISFET has been formed. Narrowing of the distance between trenches sandwiching the Schottky barrier diode therebetween is effective for reducing the field intensity on the surface of an epitaxial region in which a Schottky junction is formed (RESURF effect). This leads to improvement in avalanche capability of the Schottky barrier and as a result, enables to make the avalanche breakdown voltage of the Schottky barrier diode higher than the avalanche breakdown voltage of the power MISFET.
Japanese Patent Laid-Open No. 2003-133557 (Patent Document 3) describes a technology of forming a trench gate type power MISFET and a Schottky barrier diode over one semiconductor substrate. According to the technology described in this Patent Document 3, the avalanche breakdown voltage of the Schottky barrier diode is made higher than the avalanche breakdown voltage of the power MISFET. Described specifically, an n− type semiconductor layer (1b) is formed over a semiconductor substrate. In a Schottky barrier diode formation region, an electrode (14) is formed over this n− type semiconductor layer (1b) to form a Schottky barrier diode. In the power MISFET formation region, on the other hand, the n− type semiconductor layer (1b) and a p− type semiconductor region (4) which is a channel region are not brought into contact, but an n type semiconductor region (17) is formed so as to be brought into direct contact with the p− type semiconductor region (4) which is a channel region. This n type semiconductor region (17) is formed so as to have a doping concentration higher than that of the n− type semiconductor layer (1b). By employing such a configuration, the avalanche breakdown voltage of the power MISFET is determined by a pn junction between the n type semiconductor region (17) and the p− type semiconductor region (4) which is a channel region. Since the doping concentration of the n type semiconductor region (17) forming a pn junction with the channel region (p− type semiconductor region (4)) of the power MISFET is higher than that of the n− type semiconductor layer (1b) configuring the Schottky barrier diode, the avalanche breakdown voltage of the Schottky barrier diode can be made higher than the avalanche breakdown voltage of the power MISFET.